Datasheet

PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 8 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.5 Reading the port registers
In order to read data from the PCA9574, the bus master must first send the PCA9574
address with the least significant bit set to a logic 0 (see Figure 5
for device address). The
command byte is sent after the address and determines which register will be accessed.
After a restart, the device address is sent again but this time, the least significant bit is set
to logic 1. Data from the register defined by the command byte will then be sent by the
PCA9574. Data is clocked into the register on the falling edge of the acknowledge clock
pulse. After the first byte is read, additional bytes may be read using the auto-increment
feature.
7.5.1 Register 0 - Input port register
This register is read-only. It reflects the incoming logic levels of the pins, regardless of
whether the pin is defined as an input or an output by the Configuration register. Writes to
this register will be acknowledged but will have no effect.
The default ‘X’ is determined by the externally applied logic level.
7.5.2 Register 1 - Polarity inversion register
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5. Register 0 - Input port register (address 00h) bit description
Bit Symbol Access Value Description
7 I0.7 read only X determined by externally applied logic level
6 I0.6 read only X
5 I0.5 read only X
4 I0.4 read only X
3 I0.3 read only X
2 I0.2 read only X
1 I0.1 read only X
0 I0.0 read only X
Table 6. Register 1 - Polarity inversion register (address 01h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 N0.7 R/W 0* inverts polarity of Input port register data
0 = Input port register data retained (default value)
1 = Input port register data inverted
6N0.6 R/W 0*
5N0.5 R/W 0*
4N0.4 R/W 0*
3N0.3 R/W 0*
2N0.2 R/W 0*
1N0.1 R/W 0*
0N0.0 R/W 0*