Datasheet

PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 6 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
6.2 Pin description
[1] HVQFN16 package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
7. Functional description
7.1 Device address
Following a START condition the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9574 is shown in Figure 5
. Slave address pin A0 chooses 1 of 2 slave addresses:
40h or 42h.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while logic 0 selects a write operation.
Table 3. Pin description
Symbol Pin Type Description
TSSOP16 HVQFN16
INT
1 15 O active LOW interrupt output;
active LOW SMBus alert output
A0 2 16 I address input
RESET
3 1 I active LOW reset input
P0 4 2 I/O input/output 0
P1 5 3 I/O input/output 1
P2 6 4 I/O input/output 2
P3 7 5 I/O input/output 3
V
SS
86
[1]
ground supply ground
V
DD(IO)
9 7 power supply I/O bank supply voltage
P4 10 8 I/O input/output 4
P5 11 9 I/O input/output 5
P6 12 10 I/O input/output 6
P7 13 11 I/O input/output 7
SCL 14 12 I serial clock line
SDA 15 13 I/O serial data line
V
DD
16 14 power supply supply voltage
Fig 5. PCA9574 device address
002aad055
0 1 0 0 0 0 A0 R/W
fixed
slave address
hardware selectable