Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Device address
- 7.2 Command register
- 7.3 Register definitions
- 7.4 Writing to port registers
- 7.5 Reading the port registers
- 7.5.1 Register 0 - Input port register
- 7.5.2 Register 1 - Polarity inversion register
- 7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
- 7.5.4 Register 3 - Pull-up/pull-down selector register
- 7.5.5 Register 4 - Configuration register
- 7.5.6 Register 5 - Output port register
- 7.5.7 Register 6 - Interrupt mask register
- 7.5.8 Register 7 - Interrupt status register
- 7.6 Power-on reset
- 7.7 RESET input
- 7.8 Software reset
- 7.9 Interrupt output (INT)
- 7.10 Standby
- 8. Characteristics of the I2C-bus
- 9. Bus transactions
- 10. Application design-in information
- 11. Limiting values
- 12. Static characteristics
- 13. Dynamic characteristics
- 14. Test information
- 15. Package outline
- 16. Handling information
- 17. Soldering of SMD packages
- 18. Abbreviations
- 19. Revision history
- 20. Legal information
- 21. Contact information
- 22. Contents
PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 4 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
Fig 2. Simplified schematic of the I/Os (P0 to P7)
INTERRUPT
MASK
V
DD(IO)
P0 to P7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity
inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aad066
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
BUS-HOLD
AND
PULL-UP/PULL-DOWN
CONTROL
ESD
protection
diode
100 kΩ
V
DD(IO)