Datasheet

PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 21 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
13. Dynamic characteristics
[1] t
VD;ACK
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
Table 15. Dynamic characteristics
V
DD
= 1.1 V to 3.6 V; V
DD(IO)
= 1.1 V to 3.6 V; V
SS
=0V; T
amb
=  40  C to +85  C; unless otherwise specified.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START condition 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
VD;ACK
data valid acknowledge time
[1]
0.3 3.45 0.1 0.9 s
t
HD;DAT
data hold time 0 - 0 - ns
t
VD;DAT
data valid time
[2]
300 - 50 - ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
f
fall time of both SDA and SCL signals - 300 20 + 0.1C
b
[3]
300 ns
t
r
rise time of both SDA and SCL signals - 1000 20 + 0.1C
b
[3]
300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
-50 - 50ns
Port timing
t
v(Q)
data output valid time - 200 - 200 ns
t
su(D)
data input set-up time 150 - 150 - ns
t
h(D)
data input hold time 1 - 1 - s
Interrupt timing
t
v(INT)
valid time on pin INT -4 - 4s
t
rst(INT)
reset time on pin INT -4 - 4s
Reset
t
w(rst)
reset pulse width 6 - 6 - ns
t
rec(rst)
reset recovery time 0 - 0 - ns
t
rst(SDA)
SDA reset time Figure 19 - 450 - 450 ns
t
rst(GPIO)
GPIO reset time Figure 19 - 450 - 450 ns