Datasheet

PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 2 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
The PCA9574 is available in TSSOP16 and HVQFN16 packages and is specified over the
40 C to +85 C industrial temperature range.
2. Features and benefits
 400 kHz I
2
C-bus serial interface
 Compliant with I
2
C-bus Standard-mode (100 kHz)
 Separate supply rails for core logic and I/O bank provides voltage level shifting
 1.1 V to 3.6 V operation with level shifting feature
 Very low standby current: < 1 A
 8 configurable I/O pins that default to inputs at power-up
 Outputs:
 Totem pole: 1 mA source and 3 mA sink
 Independently programmable 100 k pull-up or pull-down for each I/O pin
 Open-drain active LOW interrupt (INT
) output pin allows monitoring of logic level
change of pins programmed as inputs
 Inputs:
 Programmable bus hold provides valid logic level when inputs are not actively
driven
 Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up
 Polarity inversion register allows inversion of the polarity of the I/O pins when read
 Active LOW reset (RESET
) input pin resets device to power-up default state
 GPIO All Call address allows programming of more than one device at the same time
with the same parameters
 2 programmable slave addresses using 1 address pin
 40 C to +85 C operation
 ESD protection exceeds 7000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: TSSOP16 and HVQFN16
3. Applications
 Cell phones
 Media players
 Multi voltage environments
 Battery operated mobile gadgets
 Motherboards
 Servers
 RAID systems
 Industrial control
 Medical equipment
 PLCs