Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Device address
- 7.2 Command register
- 7.3 Register definitions
- 7.4 Writing to port registers
- 7.5 Reading the port registers
- 7.5.1 Register 0 - Input port register
- 7.5.2 Register 1 - Polarity inversion register
- 7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
- 7.5.4 Register 3 - Pull-up/pull-down selector register
- 7.5.5 Register 4 - Configuration register
- 7.5.6 Register 5 - Output port register
- 7.5.7 Register 6 - Interrupt mask register
- 7.5.8 Register 7 - Interrupt status register
- 7.6 Power-on reset
- 7.7 RESET input
- 7.8 Software reset
- 7.9 Interrupt output (INT)
- 7.10 Standby
- 8. Characteristics of the I2C-bus
- 9. Bus transactions
- 10. Application design-in information
- 11. Limiting values
- 12. Static characteristics
- 13. Dynamic characteristics
- 14. Test information
- 15. Package outline
- 16. Handling information
- 17. Soldering of SMD packages
- 18. Abbreviations
- 19. Revision history
- 20. Legal information
- 21. Contact information
- 22. Contents
PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 19 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
12. Static characteristics
Table 14. Static characteristics
V
DD
= 1.1 V to 3.6 V; V
DD(IO)
= 1.1 V to 3.6 V; V
SS
=0V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DD
supply voltage 1.1 - 3.6 V
V
DD(IO)
input/output supply voltage 1.1 - V
DD
+0.5 V
I
DD
supply current operating mode; V
DD
=3.6V;
no load; f
SCL
= 100 kHz; I/O = inputs
- 135 200 A
I
stbL
LOW-level standby current Standby mode; V
DD
= 3.6 V; no load;
V
I
=V
SS
; f
SCL
= 0 kHz; I/O = inputs
-0.251 A
I
stbH
HIGH-level standby current Standby mode; V
DD
= 3.6 V; no load;
V
I
=V
DD
; f
SCL
= 0 kHz; I/O = inputs
-0.251 A
V
POR
power-on reset voltage no load; V
I
=V
DD
or V
SS
(rising V
DD
)- 0.81.0 V
Input SCL; input/output SDA
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-3.6 V
I
OL
LOW-level output current V
OL
=0.2V; V
DD
=1.1V 1 - - mA
V
OL
=0.4V; V
DD
=2.3V 3 - - mA
I
L
leakage current V
I
=V
DD
or V
SS
1-+1 A
C
i
input capacitance V
I
=V
SS
-610pF
I/Os
V
IL
LOW-level input voltage 0.5 - +0.3V
DD(IO)
V
V
IH
HIGH-level input voltage 0.7V
DD(IO)
-3.6 V
I
OH
HIGH-level output current V
OH
=0.9V; V
DD(IO)
=1.1V 1 - - mA
I
OL
LOW-level output current V
OL
=0.2V; V
DD(IO)
=1.1V 1 - - mA
V
OL
=0.5V; V
DD(IO)
=3.6V 2 3 - mA
V
OH
HIGH-level output voltage I
OH
= 1mA; V
DD(IO)
= 1.1 V 0.8 - - V
I
LIH
HIGH-level input leakage
current
V
DD(IO)
=3.6V; V
I
=V
DD(IO)
--1 A
I
LIL
LOW-level input leakage
current
V
DD(IO)
=3.6V; V
I
=V
SS
--1 A
C
i
input capacitance - 3.7 5 pF
C
o
output capacitance - 3.7 5 pF
Interrupt INT
I
OL
LOW-level output current V
OL
=0.4V; V
DD
=1.1V 3 - - mA
Select input A0; RESET
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-3.6 V
I
LI
input leakage current V
I
=V
DD
or V
SS
1-+1 A