Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 Device address
- 7.2 Command register
- 7.3 Register definitions
- 7.4 Writing to port registers
- 7.5 Reading the port registers
- 7.5.1 Register 0 - Input port register
- 7.5.2 Register 1 - Polarity inversion register
- 7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
- 7.5.4 Register 3 - Pull-up/pull-down selector register
- 7.5.5 Register 4 - Configuration register
- 7.5.6 Register 5 - Output port register
- 7.5.7 Register 6 - Interrupt mask register
- 7.5.8 Register 7 - Interrupt status register
- 7.6 Power-on reset
- 7.7 RESET input
- 7.8 Software reset
- 7.9 Interrupt output (INT)
- 7.10 Standby
- 8. Characteristics of the I2C-bus
- 9. Bus transactions
- 10. Application design-in information
- 11. Limiting values
- 12. Static characteristics
- 13. Dynamic characteristics
- 14. Test information
- 15. Package outline
- 16. Handling information
- 17. Soldering of SMD packages
- 18. Abbreviations
- 19. Revision history
- 20. Legal information
- 21. Contact information
- 22. Contents
PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 25 September 2014 10 of 32
NXP Semiconductors
PCA9574
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
7.5.4 Register 3 - Pull-up/pull-down selector register
When bus-hold feature is not selected and bit 1 of Register 2 is set to logic 1, the I/O port
can be configured to have pull-up or pull-down by programming the pull-up/pull-down
register. Setting a bit to logic 1 will select a 100 k pull-up resistor for that I/O pin. Setting
a bit to logic 0 will select a 100 k pull-down resistor for that I/O pin. If the bus-hold
feature is enabled, writing to this register will have no effect on pull-up/pull-down
selection.
7.5.5 Register 4 - Configuration register
This register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port pin is enabled as an input with high-impedance
output driver. If a bit in this register is cleared (written with logic 0), the corresponding port
pin is enabled as an output. At reset, the device’s ports are inputs.
Table 8. Register 3 - Pull-up/pull-down selector register (address 03h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 P0.7 R/W 1* configures I/O port pin to have pull-up or pull-down when
bus-hold feature not selected and bit 1 of Register 2 is
logic 1
0 = selects a 100 k pull-down resistor for that I/O pin
1 = selects a 100 k pull-up resistor for that I/O pin
(default value)
6P0.6R/W1*
5P0.5R/W1*
4P0.4R/W1*
3P0.3R/W1*
2P0.2R/W1*
1P0.1R/W1*
0P0.0R/W1*
Table 9. Register 4 - Configuration register (address 04h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 C0.7 R/W 1* configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6 C0.6 R/W 1*
5 C0.5 R/W 1*
4 C0.4 R/W 1*
3 C0.3 R/W 1*
2 C0.2 R/W 1*
1 C0.1 R/W 1*
0 C0.0 R/W 1*