Datasheet
PCA9570 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 17 September 2014 17 of 32
NXP Semiconductors
PCA9570
Remote 4-bit general purpose outputs for 1 MHz I
2
C-bus
14. Power-on reset requirements
In the event of a glitch or data corruption, the device can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
[1] Level that V
DD
can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when t
gw(VDD)
=1s.
[2] Glitch width that does not cause a functional disruption when V
DD
= 1.8 V to 3.6 V, V
DD(gl)
=0.5 V
DD
;
V
DD
= 1.1 V to 1.8 V, V
DD(gl)
=V
DD
0.9 V.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
w(gl)VDD
) and glitch height (V
DD(gl)
) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 22
and Table 8 provide more information on
how to measure these specifications.
Fig 21. V
DD
is lowered below 0.6 V and then ramped up to V
DD
002aah307
V
DD
time
ramp-up ramp-down
(dV/dt)
r
(dV/dt)
f
re-ramp-up
(dV/dt)
r
time to re-ramp
when V
DD
drops to V
SS
t
d(rst)
Table 8. Recommended supply sequencing and ramp rates
T
amb
=25
C (unless otherwise noted). Not tested; specified by design.
Symbol Parameter Condition Min Typ Max Unit
(dV/dt)
f
fall rate of change of voltage Figure 21 0.1 - 2000 ms
(dV/dt)
r
rise rate of change of voltage Figure 21 0.1 - 2000 ms
t
d(rst)
reset delay time Figure 21; when V
DD
drops to V
SS
1- - s
V
DD(gl)
glitch supply voltage difference Figure 22
[1]
V
DD
= 2.1 V to 3.6 V - - 1.2 V
V
DD
= 1.1 V to 2.1 V - - V
DD
0.9 V
t
w(gl)VDD
supply voltage glitch pulse width Figure 22
[2]
--10 s
V
POR(trip)
power-on reset trip voltage rising V
DD
-0.71.0 V
Fig 22. Glitch width and glitch height
002aah309
V
DD
time
t
w(gl)VDD
∆V
DD(gl)