Datasheet
PCA9570 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 17 September 2014 16 of 32
NXP Semiconductors
PCA9570
Remote 4-bit general purpose outputs for 1 MHz I
2
C-bus
13. Dynamic characteristics
[1] Fm+ mode on a non-standard, lightly loaded bus (<100 pF).
[2] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[4] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Table 7. Dynamic characteristics
V
DD
= 1.1 V to 3.6 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode
I
2
C-bus
1MHz
I
2
C-bus
[1]
Unit
Min Max Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 0 1000 kHz
t
BUF
bus free time between a
STOP and
STARTcondition
4.7 - 1.3 - 0.5 - s
t
HD;STA
hold time (repeated)
START condition
4.0 - 0.6 - 0.26 - s
t
SU;STA
set-up time for a repeated
START condition
4.7 - 0.6 - 0.26 - s
t
SU;STO
set-up time for
STOP condition
4.0 - 0.6 - 0.26 - s
t
HD;DAT
data hold time 0 - 0 - 0 - ns
t
VD;ACK
data valid acknowledge
time
[2]
- 3.45 - 0.9 - 0.45 s
t
VD;DAT
data valid time
[3]
- 3.45 - 0.9 - 0.45 s
t
SU;DAT
data set-up time 250 - 100 - 50 - ns
t
LOW
LOW period of the
SCL clock
4.7 - 1.3 - 0.5 - s
t
HIGH
HIGH period of the
SCL clock
4.0 - 0.6 - 0.26 - s
t
f
fall time of both SDA and
SCL signals
-300 20
(V
DD
/5.5V)
300 20
(V
DD
/5.5V)
120 ns
t
r
rise time of both SDA and
SCL signals
- 1000 20 300 - 120 ns
t
SP
pulse width of spikes that
must be suppressed by
the input filter
[4]
-50 - 50 - 50ns
Port timing
t
v(Q)
data output valid time - 200 - 200 - 200 ns