Datasheet

Product data sheet Rev. 7 — 10 December 2013 7 of 30

NXP Semiconductors

PCA9557

8-bit I

C-bus and SMBus I/O port with reset

7. Functional description

Refer to Figure 1 “Block diagram of PCA9557”.

7.1 Device address

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9557 is shown in Figure 8

. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

7.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9557, which will be stored in the control register. This register can be

written and read via the I

C-bus.

Fig 8. PCA9557 device address

002aad279

0 0 1 1 A2 A1 A0 R/W

fixed

slave address

programmable

Fig 9. Control register

Table 4. Register definition

D1 D0 Name Access Description

0 0 Register 0 read-only Input port register

0 1 Register 1 read/write Output port register

1 0 Register 2 read/write Polarity inversion register

1 1 Register 3 read/write Configuration register

002aad280

0 0 0 0 0 0 D1 D0

76543210bit: