Datasheet

PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 12 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
Fig 16. Read from register
0 1 1 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aad283
A
acknowledge
from slave
SDA
A P
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 A
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
command byte
0 1 1 A2 A1 A00
Remark: This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge
phase is valid (output mode). Input data is lost.
Fig 17. Read input port register
0 1 1 A2 A1 A0 1 AS0
START condition R/W acknowledge
from slave
002aad284
A
acknowledge
from master
SDA NA
read from
port
data into
port
P
t
h(D)
data from port
no acknowledge
from master
data from port
DATA 4
slave address
DATA 1
STOP
condition
DATA 2 DATA 3 DATA 4
t
su(D)
DATA 1