Datasheet

PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 11 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
8.4 Bus transactions
Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14
and Figure 15
). Data is read from the PCA9557 registers using Read and Receive Byte
transfers (see Figure 16
and Figure 17).
Fig 13. Acknowledgement on the I
2
C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
Fig 14. Write to output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aad281
00000010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to port
0 1 1 A2 A1 A00
P
STOP
condition
Fig 15. Write to I/O configuration or polarity inversion registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aad282
0000011/00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA A
acknowledge
from slave
data to register
0 1 1 A2 A1 A00
P
STOP
condition