Datasheet

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PCA9555_8 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 08 — 22 October 2009 12 of 34 NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read Input Port register).
Fig 13. Read Input port register, scenario 1
1 0 0 A2 A1 A0 1 AS0
START condition
R/W
acknowledge
from slave
002aac223
A
SCL
SDA A
read from port 0
P
987654321
I0.xslave address
STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
65432107 65432107 65432107 65432107
INT
t
v(INT_N)
t
rst(INT_N)