Datasheet

PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 9 — 19 March 2013 9 of 35
NXP Semiconductors
PCA9554; PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read.
Note that changing an I/O from and output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 k typ.) to V
DD
. The input voltage may be
raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either V
DD
or V
SS
.
Remark: At power-on reset, all registers return to default values.
Fig 8. Simplified schematic of IO0 to IO7
V
DD
IO0 to IO7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity inversion
register data
002aac493
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
100 kΩ