Datasheet
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 9 — 19 March 2013 14 of 35
NXP Semiconductors
PCA9554; PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
[1] V
DD
must be lowered to 0.2 V for at least 5 s in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
10. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data output to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
Select inputs A0, A1, A2
V
IL
LOW-level input voltage 0.5 - 0.8 V
V
IH
HIGH-level input voltage 2.0 - 5.5 V
I
LI
input leakage current 1- 1 A
Table 10. Static characteristics …continued
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 11. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START condition 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
HD;DAT
data hold time 0 - 0 - s
t
VD;ACK
data valid acknowledge time
[1]
0.3 3.45 0.1 0.9 s
t
VD;DAT
data valid time
[2]
300 - 50 - ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
r
rise time of both SDA and SCL signals - 1000 20 + 0.1C
b
[3]
300 ns
t
f
fall time of both SDA and SCL signals - 300 20 + 0.1C
b
[3]
300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
- 50 - 50 ns
Port timing
t
v(Q)
data output valid time - 200 - 200 ns
t
su(D)
data input set-up time 100 - 100 - ns
t
h(D)
data input hold time 1 - 1 - s
Interrupt timing
t
v(INT_N)
valid time on pin INT -4 - 4s
t
rst(INT_N)
reset time on pin INT -4 - 4s