Datasheet

PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 9 — 19 March 2013 11 of 35
NXP Semiconductors
PCA9554; PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
Fig 13. Read from register
1 0 0 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aac474
A
acknowledge
from slave
SDA
A P
command byte
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 0 0 A2 A1 A0 1 A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Fig 14. Read Input Port register
1 0 0 A2 A1 A0 1 AS0
START condition R/W
acknowledge
from slave
002aac475
A
acknowledge
from master
SCL
SDA
NA
read from
port
data into
port
P
t
h(D)
987654321
data from port
no acknowledge
from master
data from port
DATA 4
slave address
DATA 1
STOP
condition
DATA 2 DATA 3 DATA 4
t
su(D)
INT
t
v(INT_N)
t
rst(INT_N)