Datasheet

PCA9546A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 30 April 2014 6 of 30
NXP Semiconductors
PCA9546A
4-channel I
2
C-bus switch with reset
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master sends a
byte to the PCA9546A, which is stored in the control register. If the PCA9546A receives
multiple bytes, it saves the last byte received. This register can be written and read via the
I
2
C-bus.
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9546A has been addressed. The
4 LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I
2
C-bus. This ensures that all SCx/SDx lines are in a HIGH state when the
channel is made active, so that no false conditions are generated at the time of
connection.
Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1,
B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and
channel 2 are enabled. Care should be taken not to exceed the maximum bus
capacitance.
Fig 6. Control register
002aab190
X X X X B3 B2 B1 B0
channel selection bits
(read/write)
76543210
channel 0
channel 1
channel 2
channel 3
Table 4. Control register: Write—channel selection; Read—channel status
D7 D6 D5 D4 B3 B2 B1 B0 Command
XXXXXXX
0 channel 0 disabled
1 channel 0 enabled
XXXXXX
0
X
channel 1 disabled
1 channel 1 enabled
XXXXX
0
XX
channel 2 disabled
1 channel 2 enabled
XXXX
0
XXX
channel 3 disabled
1 channel 3 enabled
0 0 0 0 0 0 0 0 no channel selected;
power-up/reset default state