Datasheet

PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9 — 5 May 2014 6 of 32
NXP Semiconductors
PCA9545A/45B/45C
4-channel I
2
C-bus switch with interrupt logic and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9545A/45B/45C”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9545A is shown in Figure 5
. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read is selected while a logic 0 selects a write operation.
The PCA9545BPW and PCA9545CPW are alternate address versions if needed for larger
systems or to resolve conflicts. The data sheet references the PCA9545A, but the
PCA9545B and PCA9545C function identically except for the slave address.
Fig 5. Slave address PCA9545A
Fig 6. Slave address PCA9545B Fig 7. Slave address PCA9545C
002aab169
1 1 1 0 0 A1 A0 R/W
fixed hardware
selectable
002aab835
1 1 0 1 0 A1 A0 R/W
fixed hardware
selectable
002aab836
1 0 1 1 0 A1 A0 R/W
fixed hardware
selectable