Datasheet

PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9 — 5 May 2014 12 of 32
NXP Semiconductors
PCA9545A/45B/45C
4-channel I
2
C-bus switch with interrupt logic and reset
7.5 Bus transactions
Data is transmitted to the PCA9545A/45B/45C control register using the Write mode as
shown in Figure 14
.
Data is read from PCA9545A/45B/45C using the Read mode as shown in Figure 15.
Fig 14. Write control register
Fig 15. Read control register
002aab172
XXXXB3B2B1B01 1 0 0 A1 A0 0 AS 1 A P
slave address
START condition R/W acknowledge
from slave
acknowledge
from slave
control register
SDA
STOP condition
002aab173
INT3 INT2 INT1 INT0 B3 B2 B1 B01 1 0 0 A1 A0 1 AS 1 NA P
slave address
START condition R/W acknowledge
from slave
no acknowledge
from master
control register
SDA
STOP condition
last byte