Datasheet

PCA9544A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 23 April 2014 8 of 31
NXP Semiconductors
PCA9544A
4-channel I
2
C-bus multiplexer with interrupt logic
6.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9544A in
a reset condition until V
DD
has reached V
POR
. At this point, the reset condition is released
and the PCA9544A registers and I
2
C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, V
DD
must be
lowered below 0.2 V for at least 5 s in order to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9544A are constructed such that the V
DD
voltage can
be used to limit the maximum voltage that is passed from one I
2
C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 12 “
Dynamic characteristics” of this
data sheet). In order for the PCA9544A to act as a voltage translator, the V
o(sw)
voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then V
o(sw)
should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7
, we see that V
o(sw)(max)
is at 2.7 V when the PCA9544A supply voltage is 3.5 V or
lower so the PCA9544A supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see Figure 14
).
More Information can be found in Application Note AN262, PCA954X family of I
2
C/SMBus
multiplexers and switches.
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage versus supply voltage
V
DD
(V)
2.0 5.54.53.0 4.0
002aaa964
3.0
2.0
4.0
5.0
V
o(sw)
(V)
1.0
3.5 5.02.5
(1)
(2)
(3)