Datasheet

PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 5 of 28
NXP Semiconductors
PCA9543A/43B
2-channel I
2
C-bus switch with interrupt logic and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9543A/43B”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9543A/43B is shown in Figure 4
. To conserve power,
no internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
The PCA9543B is an alternate address version, if needed for larger systems or to resolve
address conflicts. The data sheet will reference the PCA9543A, but the PCA9543B
functions identically except for the slave address.
6.1.1 Address maps
Fig 4. Slave address PCA9543A
Fig 5. Slave address PCA9543B
002aab169
1 1 1 0 0 A1 A0 R/W
fixed hardware
selectable
002aab799
1 1 1 1 0 A1 A0 R/W
fixed hardware
selectable
Table 4. PCA9543A address map
Pin connectivity Address of PCA9543A Address byte value 7-bit
hexadecimal
address
without R/W
A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read
V
SS
V
SS
1110000 - E0h E1h 70h
V
SS
V
DD
1110001 - E2h E3h 71h
V
DD
V
SS
1110010 - E4h E5h 72h
V
DD
V
DD
1110011 - E6h E7h 73h