Datasheet

PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 11 of 28
NXP Semiconductors
PCA9543A/43B
2-channel I
2
C-bus switch with interrupt logic and reset
7.5 Bus transactions
Data is transmitted to the PCA9543A/43B control register using the Write mode as shown
in Figure 12
.
Data is read from PCA9543A/43B using the Read mode as shown in Figure 13.
Fig 12. Write control register
Fig 13. Read control register
002aab182
XXXXXXB1B01 1 0 0 A1 A0 0 AS 1 A P
slave address
START condition R/W acknowledge
from slave
acknowledge
from slave
control register
SDA
STOP condition
002aab183
X X INT1 INT0 X X B1 B01 1 0 0 A1 A0 1 AS 1 NA P
slave address
START condition R/W acknowledge
from slave
no acknowledge
from master
control register
SDA
STOP condition
last byte