Manualshelf

Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsInterface ICsInterface IC - customised HVQFN 16
12345678910
PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 8 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
7.3 Interrupt Enable and Control registers description
When a master seeks control of the bus by connecting its I
2
C-bus channel to the
PCA9541A downstream channel, it has to write to the CONTROL register (Reg#01).
Bits MYBUS and BUSON allow the master to take control of the bus.
The MYBUS and the NMYBUS bits determine which master has control of the bus.
Table 9
explains which master gets control of the bus and how. There is no arbitration.
Any master can take control of the bus when it wants regardless of whether the other
master is using it or not.
The BUSON and the NBUSON bits determine whether the upstream bus is connected or
disconnected to/from the downstream bus. Table 10
explains when the upstream bus is
connected or disconnected.
Internally, the state machine does the following:
• If the combination of the BUSON and the NBUSON bits causes the upstream to be
disconnected from the downstream bus, then that is done. So in this case, the values
of the MYBUS and the NMYBUS do not matter.
• If a master was connected to the downstream bus prior to the disconnect, then an
interrupt is sent on the respective interrupt output in an attempt to let that master know
that it is no longer connected to the downstream bus. This is indicated by setting the
BUSLOST bit in the Interrupt Status Register.
• If the combination of the BUSON and the NBUSON bits causes a master to be
connected to the downstream bus and if there is no change in the BUSON bits since
when the disconnect took effect, then the master requesting the bus is connected to
the downstream bus. If it requests a bus initialization sequence, then it is performed.
• If there is no change in the combination of the BUSON and the NBUSON bits and a
new master wants the bus, then the downstream bus is disconnected from the old
master that was using it and the new master gets control of it. Again, the bus
initialization if requested is done. The appropriate interrupt signals are generated.
After a master has sent the bus control request:
1. The previous master is disconnected from the I
2
C-bus. An interrupt to the previous
master is sent through its INT
line to let it know that it lost control of the bus.
BUSLOST bit in the Interrupt Status Register is set. This interrupt can be masked by
setting the BUSLOSTMSK bit to logic 1.
Fig 7. Internal register map