Datasheet

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PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 24 April 2014 22 of 45 NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus).
Fig 15. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization requested)
002aab609
1 1 1 A3 A2 A1 A0 0
slave address
R/W
S
START condition
A
acknowledge
from slave
000AI0001
command code register
auto
increment
A
acknowledge
from slave
P
STOP
condition
A
acknowledge
from slave
data Control register
SDA_MST0
(1)
0 0 0 1 0 1 0 0
BUSINIT
BUSON
MYBUS
After the STOP condition
MASTER 1 is disconnected
from the downstream channel.
SCL_MST0
if the interrupt is not masked
(BUSLOSTMSK = 0)
INT1
123456789
SCL_SLAVE
SDA_SLAVE
A
STOP command
INT0
if the interrupt is not masked
(BUSINITMSK = 0)
PCA9541 has control of the bus
MASTER 0
has control
of the busMASTER 1 has control of the bus
MASTER 0 must wait for the 'bus free time' value
(between STOP and START) defined in the I
2
C-bus specification
before sending commands to the downstream devices.