Datasheet

PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 19 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
8. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 9
).
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see Figure 10
).
Fig 9. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 10. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition