Datasheet

PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 16 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
7.4.3 Downstream interrupt
An interrupt can also be generated by a downstream device by asserting the INT_IN pin
LOW. When INT_IN
is asserted LOW, and if both INTINMSK bits are not set to ‘1’ by
either master, INT0
and INT1 both go LOW.
By setting the INTINMSK bit to ‘1’ by a master and/or the INTINMSK bit to ‘1’ by the other
master, the interrupts are masked and the corresponding masked channels do not receive
an interrupt (INT0
and/or INT1 line does not go LOW).
7.4.4 Functional test interrupt
A master can send an interrupt to itself to test its own INT wire or send an interrupt to the
other master to test its INT
line. This is done by:
• setting the TESTON bit to ‘1’ to test its own INT line
• setting the NTESTON bit to ‘1’ to test the other master INT line
Setting the TESTON and/or NTESTON bits to ‘0’ by a master clears the interrupts.
Remark: Interrupt outputs have an open-drain structure. Interrupt input does not have any
internal pull-up resistor and must not be left floating (that is, pulled HIGH to V
DD
through
resistor) in order to avoid any undesired interrupt conditions.
7.4.5 Register 2: Interrupt Status Register (B1:B0 = 10b)
The Interrupt Status Register for both the masters is identical and is described below.
Nevertheless, there are physically 2 internal Interrupt Registers, one for each upstream
channel.
When Master 0 reads this register, the internal Interrupt Register 0 is accessed.
When Master 1 reads this register, the internal Interrupt Register 1 is accessed.
Table 13. Register 2 - Interrupt Status register (B1:B0 = 10b) bit allocation
7 6 5 4 3 2 1 0
NMYTEST MYTEST 0 0 BUSLOST BUSOK BUSINIT INTIN
Table 14. Register 2 - Interrupt Status (ISTAT) register bit description
Legend: * default value
Bit Symbol Access Value
[1]
Description
7 NMYTEST
[2]
R only 0* no interrupt generated due to NTESTON bit from the other master
(NTESTON = 0 from the other master)
[3]
1 interrupt generated due to TESTON bit from the other master
(NTESTON = 1 from the other master)
[3]
6 MYTEST
[2]
R only 0* no interrupt generated by TESTON bit (TESTON = 0)
[3]
1 interrupt generated by TESTON bit (TESTON = 1)
[3]
5 - R only 0* not used
4 - R only 0* not used
3BUSLOST
[4]
R only 0* no interrupt generated to the previous master when switching to the new one
is initiated
1 interrupt generated to the previous master when switching to the new one is
initiated