Datasheet

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PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 24 April 2014 14 of 45 NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
[1] Only the 4 LSBs are shown.
[2] x0x0 in binary = 0, 2, 8 or A in hexadecimal
x0x1 in binary = 1, 3, 9 or B in hexadecimal
x1x0 in binary = 4, 6, C or E in hexadecimal
x1x1 in binary = 5, 7, D or F in hexadecimal
[3] x can be either ‘0’ or ‘1’ since those bits are read-only bits.
Table 12. Bus control sequence
Read Control Register performed by the master Write Control Register performed by the master
Byte
read
[1]
(h)
Status NBUSON BUSON NMYBUS MYBUS Byte
written
[1][2]
(h)
Action performed
to take mastership
NBUSON
[3]
BUSON NMYBUS
[3]
MYBUS
0 bus off has control 0 0 0 0 4 bus on x 1 x 0
1 bus off no control 0 0 0 1 4 bus on, take control x 1 x 0
2 bus off no control 0 0 1 0 5 bus on, take control x 1 x 1
3 bus off has control 0 0 1 1 5 bus on x 1 x 1
4 bus on has control 0 1 0 0 - no change no write required
5 bus on no control 0 1 0 1 4 take control x 1 x 0
6 bus on no control 0 1 1 0 5 take control x 1 x 1
7 bus on has control 0 1 1 1 - no change no write required
8 bus on has control 1 0 0 0 - no change no write required
9 bus on no control 1 0 0 1 0 take control x 0 x 0
A bus on no control 1 0 1 0 1 take control x 0 x 1
B bus on has control 1 0 1 1 - no change no write required
C bus off has control 1 1 0 0 0 bus on x 0 x 0
D bus off no control 1 1 0 1 0 bus on, take control x 0 x 0
E bus off no control 1 1 1 0 1 bus on, take control x 0 x 1
F bus off has control 1 1 1 1 1 bus on x 0 x 1