Datasheet

PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 13 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
Current status of the I
2
C-bus is determined by the bits MYBUS, NMYBUS, BUSON and
NBUSON is one of the following:
• The master reading its Control Register does not have control and the I
2
C-bus is off.
• The master reading its Control Register does not have control and the I
2
C-bus is on.
• The master reading its Control Register has control and the I
2
C-bus is off.
• The master reading its Control Register has control and the I
2
C-bus is on.
‘I
2
C-bus off’ means that upstream and downstream channels are not connected together.
‘I
2
C-bus on’ means that upstream and downstream channels are connected together.
Remark: Only the 4 LSBs of the Control Register are described in Table 12
since only
those bits control the I
2
C-bus control. The logic value for the 4 MSBs is specific to the
application and are not discussed in the table.
The read sequence is performed by the master as:
S - 111xxxx0 - 000x0001 - Sr - 111xxxx1 - DataRead - P
The write sequence is performed by the master as:
S - 111xxxx0 - 000x0001 - DataWritten - P