Datasheet

PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 10 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
7.3.1 Register 0: Interrupt Enable (IE) register (B1:B0 = 00b)
This register allows a master to read and/or write (if needed) Mask options for its own
channel.
The Interrupt Enable register described below is identical for both the masters.
Nevertheless, there are physically 2 internal Interrupt Enable registers, one for each
upstream channel. When Master 0 reads/writes in this register, the internal Interrupt
Enable Register 0 is accessed. When Master 1 reads/writes in this register, the internal
Interrupt Enable Register 1 is accessed.
[1] Default values are the same for PCA9541A/01, PCA9541A/03.
Table 5. Register 0 - Interrupt Enable (IE) register (B1:B0 = 00b) bit allocation
7 6 5 4 3 2 1 0
0 0 0 0 BUSLOSTMSK BUSOKMSK BUSINITMSK INTINMSK
Table 6. Register 0 - Interrupt Enable (IE) register bit description
Legend: * default value
Bit Symbol Access Value
[1]
Description
7:4 - R only 0* not used
3 BUSLOSTMSK R/W 0* An interrupt on INT
will be generated after the other master has been
disconnected.
1 An interrupt on INT
will not be generated after the other master has been
disconnected.
2 BUSOKMSK R/W 0* After connection is requested and Bus Initialization not requested
(BUSINIT = 0), an interrupt on INT
will be generated when a non-idle situation
has been detected on the downstream slave channel by the bus sensor at the
switching moment.
Remark: Channel switching is done automatically after the STOP command.
1 After connection is requested and Bus Initialization not requested
(BUSINIT = 0), an interrupt on INT
will not be generated when a non-idle
situation has been detected on the downstream slave channel by the bus
sensor at the switching moment (masked).
Remark: Channel switching is done automatically after the STOP command.
1 BUSINITMSK R/W 0* After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT
will be generated when the bus initialization is done.
Remark: Channel switching is done after bus initialization completed.
1 After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT
will not be generated when the bus initialization is done
(masked).
Remark: Channel switching is done after bus initialization completed.
0 INTINMSK R/W 0* Interrupt on INT_IN generates an interrupt on INT.
1 Interrupt on INT_IN
does not generate an interrupt on INT (masked)