Datasheet

PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 21 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
8.5 Bus transactions
Remark: If a third data byte is sent, it is not acknowledged by the PCA9541A.
Remark: If a fourth data byte is read, the first register is accessed.
Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit
002aab607
1 1 1 A3 A2 A1 A0 0
slave address
R/W
S
START condition
A
acknowledge
from slave
00010000
command code register
auto
increment
A
acknowledge
from slave
A P
STOP
condition
A
acknowledge
from slave
acknowledge
from slave
data
Interrupt Enable (IE)
register
data control register
(CONTROL)
(1) xx = 00: Interrupt Enable register
xx = 01: Control register
xx = 10: INT register
(2) xx = 00: Control register
xx = 01: INT register
xx = 10: Interrupt Enable register
(3) xx = 00: INT register
xx = 01: Interrupt Enable register
xx = 10: Control register
Fig 14. Read the 3 registers using the Auto-Increment (AI) bit
002aab608
1 1 1 A3 A2 A1 A0 0
slave address
R/W
S
START condition
A
acknowledge
from slave
000100xx
command code register
access to register
xx = 00, 01, or 10
auto
increment
A
acknowledge
from slave
A P
STOP
condition
A
no acknowledge
from master
acknowledge
from master
(1) (2)
Sr
re-START
condition
1 1 1 A3 A2 A1 A0 1
slave address
R/W
A
acknowledge
from slave
A
acknowledge
from master
(3)