Datasheet

PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 2 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin
LOW resets the I
2
C-bus state machine and configures the device to its default state as
does the internal Power-On Reset (POR) function.
2. Features and benefits
 2-to-1 bidirectional master selector
 I
2
C-bus interface logic; compatible with SMBus standards
 PCA9541A/01 powers up with Channel 0 selected
 PCA9541A/03 powers up with no channel selected and either master can take control
of the bus
 Active LOW interrupt input
 2 active LOW interrupt outputs
 Active LOW reset input
 4 address pins allowing up to 16 devices on the I
2
C-bus
 Channel selection via I
2
C-bus
 Bus initialization/recovery function
 Bus traffic sensor
 Low R
on
switches
 Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
 No glitch on power-up
 Supports hot insertion
 Software identical for both masters
 Low standby current
 Operating power supply voltage range of 2.3 V to 5.5 V
 6.0 V tolerant inputs
 0 Hz to 400 kHz clock frequency
 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: SO16, TSSOP16, HVQFN16
3. Applications
 High reliability systems with dual masters
 Gatekeeper multiplexer on long single bus
 Bus initialization/recovery for slave devices without hardware reset
 Allows masters without arbitration logic to share resources