Datasheet
PCA9540B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 5 May 2014 7 of 27
NXP Semiconductors
PCA9540B
2-channel I
2
C-bus multiplexer
Figure 7, we see that V
o(sw)(max)
is at 2.7 V when the PCA9540B supply voltage is 3.5 V or
lower so the PCA9540B supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see Figure 14
).
More Information can be found in application note AN262, “PCA954X family of I
2
C/SMBus
multiplexers and switches”.
7. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 8
).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9
).
Fig 8. Bit transfer
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Fig 9. Definition of START and STOP conditions
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