Datasheet
PCA9540B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 5 May 2014 6 of 27
NXP Semiconductors
PCA9540B
2-channel I
2
C-bus multiplexer
6.3 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9540B in
a reset condition until V
DD
has reached V
POR
. At this point, the reset condition is released
and the PCA9540B registers and I
2
C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, V
DD
must be
lowered below 0.2 V for at least 5 s in order to reset the device.
6.4 Voltage translation
The pass gate transistors of the PCA9540B are constructed such that the V
DD
voltage can
be used to limit the maximum voltage that is passed from one I
2
C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “
Static characteristics” of this
data sheet). In order for the PCA9540B to act as a voltage translator, the V
o(sw)
voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then V
o(sw)
should be
equal to or below 2.7 V to clamp the downstream bus voltages effectively. Looking at
Table 4. Control register: Write — channel selection; Read — channel status
D7 D6 D5 D4 D3 B2 B1 B0 Command
X X X X X 0 X X no channel selected
X X X X X 1 0 0 channel 0 enabled
X X X X X 1 0 1 channel 1 enabled
X X X X X 1 1 X no channel selected
0 0 0 0 0 0 0 0 no channel selected;
power-up default state
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage versus supply voltage
9
''
9
DDD
9
RVZ
9