Datasheet
PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 26 November 2014 5 of 38
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
Fig 5. Pin configuration for SO24 Fig 6. Pin configuration for TSSOP24
Fig 7. Pin configuration for HVQFN24
PCA9539D
INT V
DD
A1 SDA
RESET SCL
IO0_0 A0
IO0_1 IO1_7
IO0_2 IO1_6
IO0_3 IO1_5
IO0_4 IO1_4
IO0_5 IO1_3
IO0_6 IO1_2
IO0_7 IO1_1
V
SS
IO1_0
002aad719
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
INT V
DD
A1 SDA
RESET SCL
IO0_0 A0
IO0_1 IO1_7
IO0_2 IO1_6
IO0_3 IO1_5
IO0_4 IO1_4
IO0_5 IO1_3
IO0_6 IO1_2
IO0_7 IO1_1
V
SS
IO1_0
PCA9539PW
PCA9539PW/Q900
PCA9539RPW
002aad720
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
002aad721
PCA9539BS
PCA9539RBS
Transparent top view
IO1_3
IO0_4
IO0_5
IO1_4
IO0_3 IO1_5
IO0_2 IO1_6
IO0_1 IO1_7
IO0_0 A0
IO0_6
IO0_7
V
SS
IO1_0
IO1_1
IO1_2
RESET
A1
INT
V
DD
SDA
SCL
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19