Datasheet

PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 26 November 2014 24 of 38
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Rise and fall times refer to V
IL
and V
IH
.
Fig 27. I
2
C-bus timing diagram
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
002aab285
t
SU;STO
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
1 / f
SCL
t
r
t
VD;DAT
acknowledge
(A)
STOP
condition
(P)
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD