Datasheet

PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 26 November 2014 23 of 38
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Fig 24. Definition of RESET timing in PCA9539R
SDA
SCL
002aad733
t
rst
50 %
30 %
50 % 50 %
50 %
t
rec(rst)
t
w(rst)
RESET
IOn
after reset, I/Os unchanged;
device state machine reset
START
t
rst
ACK or read cycle
Fig 25. Expanded view of read input port register
Fig 26. Expanded view of write to output port register
SCL
002aad734
210 AP
70 %
30 %
SDA
input
50 %
INT
t
v(INT_N)
t
rst(INT_N)
t
h(Q)
t
su(D)
SCL
002aad735
210 AP
70 %
SDA
output
50 %
t
v(Q)