Datasheet

PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 26 November 2014 22 of 38
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
[1] t
VD;ACK
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
[4] t
v(Q)
measured from 0.7V
DD
on SCL to 50 % I/O output.
[5] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
[6] Upon reset, the full delay will be the sum of t
rst
and the RC time constant of the SDA bus.
RESET timing
t
w(rst)
reset pulse width 4 - 4 - ns
t
rec(rst)
reset recovery time 0 - 0 - ns
t
rst
reset time
[5][6]
400 - 400 - ns
Table 16. Dynamic characteristics
…continued
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
Fig 22. Definition of timing on the I
2
C-bus
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
Fig 23. Definition of RESET timing in PCA9539
SDA
SCL
002aad732
t
rst
50 %
30 %
50 % 50 %
50 %
t
rec(rst)
t
w(rst)
RESET
IOn
after reset,
I/Os reconfigured
as inputs
START
t
rst
ACK or read cycle