Datasheet

PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 26 November 2014 10 of 38
NXP Semiconductors
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
6.6 Bus transactions
6.6.1 Writing to the port registers
Data is transmitted to the PCA9539; PCA9539R by sending the device address and
setting the least significant bit to a logic 0 (see Figure 8 “
PCA9539; PCA9539R device
address”). The command byte is sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9539; PCA9539R are configured to operate as four
register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and
Configuration ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see Figure 10
and Figure 11). For example, if the first byte is
sent to Output port 1 (register 3), then the next byte will be stored in Output port 0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.
At power-on reset, all registers return to default values.
Fig 9. Simplified schematic of I/Os
V
DD
I/O pin
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aad723
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT