Datasheet
PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 26 November 2014 16 of 34
NXP Semiconductors
PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
[1] V
DD
must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
V
OH
HIGH-level output voltage I
OH
= 8 mA
V
DD
=4.5V
[3]
4.1 - - V
V
DD
=3.0V
[3]
2.5 - - V
I
OH
= 10 mA
V
DD
=4.5V
[3]
4.0 - - V
V
DD
=3.0V
[3]
2.4 - - V
I
LI
input leakage current V
I
=V
DD
=V
SS
1-+1A
C
i
input capacitance - 5 10 pF
Interrupt INT
I
OL
LOW-level output current V
OL
=0.4V 3 13 - mA
Select inputs A0, A1, RESET
V
IL
LOW-level input voltage 0.5 - +0.8 V
V
IH
HIGH-level input voltage 2.0 - 5.5 V
I
LI
input leakage current 1-+1A
Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device
…continued
V
DD
= 3.0 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +125
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit