Datasheet

PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 26 November 2014 11 of 34
NXP Semiconductors
PCA9538
8-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Fig 9. Read from register
AS
START condition R/W
acknowledge
from slave
002aae710
A
acknowledge
from slave
SDA
A P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1100A1A01A1
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
COMMAND BYTE
1100A1A01 0
data from register
DATA (last byte)
data from register
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Expanded diagram is shown in Figure 17
.
Fig 10. Read input port register
1100A1A01AS1
slave address
START condition R/W acknowledge
from slave
002aae711
data from port
A
acknowledge
from master
SDA NA
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
v(INT)
t
rst(INT)
t
h(D)
t
su(D)
12345678SCL 9
DATA 1