Datasheet

PCA9538A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 28 September 2012 7 of 37
NXP Semiconductors
PCA9538A
Low-voltage 8-bit I
2
C-bus I/O port with interrupt and reset
6.4.4 Configuration register (03h)
The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this
register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a
bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
6.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either V
DD
or V
SS
. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
Table 9. Configuration register (address 03h)
Bit 7 6 5 4 3 2 1 0
Symbol C7 C6 C5 C4 C3 C2 C1 C0
Default 11111111
On power-up or reset, all registers return to default values.
Fig 6. Simplified schematic of the I/Os (P0 to P7)
V
DD
P0 to P7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity
inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aah423
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
ESD
protection
diode