Datasheet

PCA9538A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 28 September 2012 5 of 37
NXP Semiconductors
PCA9538A
Low-voltage 8-bit I
2
C-bus I/O port with interrupt and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9538A”.
6.1 Device address
A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)
or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the
slave address (R/W
) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9538A. Two bits of this
data byte state the operation (read or write) and the internal registers (Input, Output,
Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with the lower
three bits of the Command byte are used to point to the extended features of the device
(Agile I/O). This register is write only.
[1] Undefined.
Fig 4. PCA9538A address
R/W
002aae707
1 1 1 0 0 A1 A0
slave address
fixed hardware
selectable
Fig 5. Pointer register bits
002aaf540
B7 B6 B5 B4 B3 B2 B1 B0
Table 4. Command byte
Pointer register bits Command byte
(hexadecimal)
Register Protocol Power-up
default
B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 00h Input port read byte xxxx xxxx
[1]
0 0 0 0 0 0 0 1 01h Output port read/write byte 1111 1111
0 0 0 0 0 0 1 0 02h Polarity Inversion read/write byte 0000 0000
0 0 0 0 0 0 1 1 03h Configuration read/write byte 1111 1111