Datasheet
PCA9538A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 28 September 2012 22 of 37
NXP Semiconductors
PCA9538A
Low-voltage 8-bit I
2
C-bus I/O port with interrupt and reset
13. Dynamic characteristics
[1] Minimum time for SDA to become HIGH or minimum time to wait before doing a START.
Table 15. I
2
C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 26.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode
I
2
C-bus
Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
HIGH
HIGH period of the SCL clock 4 - 0.6 - s
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
SP
pulse width of spikes that must
be suppressed by the input filter
050 0 50ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
HD;DAT
data hold time 0 - 0 - ns
t
r
rise time of both SDA and SCL signals - 1000 20 300 ns
t
f
fall time of both SDA and SCL signals - 300 20
(V
DD
/5.5V)
300 ns
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
HD;STA
hold time (repeated) START condition 4 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4 - 0.6 - s
t
VD;DAT
data valid time SCL LOW to
SDA output valid
-3.45 - 0.9s
t
VD;ACK
data valid acknowledge time ACK signal
from SCL LOW
to SDA (out) LOW
-3.45 - 0.9s
Table 16. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 29
.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode
I
2
C-bus
Unit
Min Max Min Max
t
w(rst)
reset pulse width 30 - 30 - ns
t
rec(rst)
reset recovery time 200 - 200 - ns
t
rst
reset time
[1]
600 - 600 - ns