Datasheet

PCA9538A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 28 September 2012 14 of 37
NXP Semiconductors
PCA9538A
Low-voltage 8-bit I
2
C-bus I/O port with interrupt and reset
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
w(gl)VDD
) and glitch height (V
DD(gl)
) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 17
and Table 10 provide more information on
how to measure these specifications.
V
POR
is critical to the power-on reset. V
POR
is the voltage level at which the reset condition
is released and all the registers and the I
2
C-bus/SMBus state machine are initialized to
their default states. The value of V
POR
differs based on the V
DD
being lowered to or from
0V. Figure 18
and Table 10 provide more details on this specification.
Fig 17. Glitch width and glitch height
Fig 18. Power-on reset voltage (V
POR
)
002aah331
V
DD
time
t
w(gl)VDD
∆V
DD(gl)
002aah332
POR
time
V
DD
time
V
POR
(rising V
DD
)
V
POR
(falling V
DD
)