Datasheet

PCA9538A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 28 September 2012 10 of 37
NXP Semiconductors
PCA9538A
Low-voltage 8-bit I
2
C-bus I/O port with interrupt and reset
7.2 Read commands
To read data from the PCA9538A, the bus master must first send the PCA9538A address
with the least significant bit set to a logic 0 (see Figure 4
for device address). The
command byte is sent after the address and determines which register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1.
Data from the register defined by the command byte then is sent by the PCA9538A (see
Figure 9
and Figure 10).
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limit on the number of data bytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
Fig 9. Read from register
AS
START condition R/W
acknowledge
from slave
002aah104
A
acknowledge
from slave
SDA
A P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1100A1A01A1
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
COMMAND BYTE
1100A1A01 0
data from register
DATA (last byte)
data from register
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see Figure 9
).
Fig 10. Read Input port register
1100A1A01AS1
slave address
START condition R/W acknowledge from slave
002aah105
data from port
A
acknowledge from master
SDA 1
no acknowledge
from master
read from
port
data into
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
t
v(INT)
t
rst(INT)
t
h(D)
t
su(D)
12345678SCL 9
DATA 1 DATA 5
INT is cleared by
read from port
STOP not needed
to clear INT