Datasheet

PCA9537_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 7 May 2009 8 of 24
NXP Semiconductors
PCA9537
4-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
6.7 Bus transactions
Data is transmitted to the PCA9537 registers using the write mode as shown in Figure 5
and Figure 6. Data is read from the PCA9537 registers using the read mode as shown in
Figure 7 and Figure 8. These devices do not implement an auto-increment function so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
Expanded diagram is shown in Figure 16.
Fig 5. Write to output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aae636
00000010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA 1 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to port
0010011
P
STOP
condition
Fig 6. Write to configuration or polarity inversion registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aae637
0000011/00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA DATA 1 A
data to register
acknowledge
from slave
data to register
0010011
P
STOP
condition