Datasheet

PCA9537_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 7 May 2009 14 of 24
NXP Semiconductors
PCA9537
4-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Fig 12. Definition of timing
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
Rise and fall times refer to V
IL
and V
IH
.
Fig 13. I
2
C-bus timing diagram
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
002aab285
t
SU;STO
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
1 / f
SCL
t
r
t
VD;DAT
acknowledge
(A)
STOP
condition
(P)
Fig 14. Definition of RESET timing
SDA
SCL
002aad732
t
rst
50 %
30 %
50 % 50 %
50 %
t
rec(rst)
t
w(rst)
RESET
IOn
after reset,
I/Os reconfigured
as inputs
START
t
rst
ACK or read cycle