Datasheet

PCA9536_5 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 25 January 2010 8 of 22
NXP Semiconductors
PCA9536
4-bit I
2
C-bus and SMBus I/O port
Fig 7. Write to Output Port register
0000010AS1
START condition R/W
acknowledge
from slave
002aab85
4
A
acknowledge
from slave
SCL
SDA
A
write to port
data out
from port
P
t
v(Q)
987654321
command byte
acknowledge
from slave
data to port
DATA 1
slave address
00000010
STOP
condition
data 1 valid
Fig 8. Write to Configuration register or Polarity Inversion register
0000010AS1
START condition R/W
acknowledge
from slave
002aab85
5
A
acknowledge
from slave
SCL
SDA
A
data to
register
P
987654321
command byte
acknowledge
from slave
data to register
DATA
slave address
0000001/00
STOP
condition
Fig 9. Read from register
0000010AS1
START condition R/W
acknowledge
from slave
002aab856
A
acknowledge
from slave
SDA
A P
command byte
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
0000011A1
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)