Datasheet

PCA9535_PCA9535C_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 15 September 2008 20 of 31
NXP Semiconductors
PCA9535; PCA9535C
16-bit I
2
C-bus and SMBus, low power I/O port with interrupt
Fig 20. Definition of timing on the I
2
C-bus
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
Rise and fall times refer to V
IL
and V
IH
.
Fig 21. I
2
C-bus timing diagram
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
002aab175
t
SU;STO
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
1
/f
SCL
t
r
t
VD;DAT
Fig 22. t
v(Q)
timing
t
v(Q)
SCL
002aad327
IOn
t
v(Q)
SCL
IOn