Datasheet

PCA9535A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 11 September 2012 5 of 38
NXP Semiconductors
PCA9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt
6. Functional description
Refer to Figure 1 “Block diagram of PCA9535A”.
6.1 Device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W
) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9535A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
[1] Undefined.
Fig 4. PCA9535A device address
R/W
002aah371
0 1 0 0 A2 A1 A0
hardware
selectable
slave address
fixed
Fig 5. Pointer register bits
002aaf540
B7 B6 B5 B4 B3 B2 B1 B0
Table 4. Command byte
Pointer register bits Command byte
(hexadecimal)
Register Protocol Power-up
default
B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 00h Input port 0 read byte xxxx xxxx
[1]
0 0 0 0 0 0 0 1 01h Input port 1 read byte xxxx xxxx
0 0 0 0 0 0 1 0 02h Output port 0 read/write byte 1111 1111
0 0 0 0 0 0 1 1 03h Output port 1 read/write byte 1111 1111
0 0 0 0 0 1 0 0 04h Polarity Inversion port 0 read/write byte 0000 0000
0 0 0 0 0 1 0 1 05h Polarity Inversion port 1 read/write byte 0000 0000
0 0 0 0 0 1 1 0 06h Configuration port 0 read/write byte 1111 1111
0 0 0 0 0 1 1 1 07h Configuration port 1 read/write byte 1111 1111